high-level synthesis造句
例句與造句
- Synthesis and optimization of loop in high - level synthesis
高級(jí)綜合中循環(huán)的綜合方法研究 - Language requirements for high - level synthesis
高級(jí)綜合的語言要求 - High - level synthesis of timing and synchronization in i o communication
通訊中時(shí)序和同步的高級(jí)綜合 - High - level synthesis ( hls ) systems for digital ic are playing such a role
高層次綜合( hls )系統(tǒng)就起著這樣的作用。 - This paper researched the asic design in the automation system of a kind of auv with high - level design method based on vhdl high - level synthesis
本文采用基于vhdl高級(jí)綜合的高層次設(shè)計(jì)方法對某型水下航行器自控系統(tǒng)的集成設(shè)計(jì)進(jìn)行了研究。 - It's difficult to find high-level synthesis in a sentence. 用high-level synthesis造句挺難的
- All the modules of risc mcu core were described with verilog hdl and synthesized with high - level synthesis eda tools . then the risc mcu was implemented in fpga device
所有模塊都采用verilog硬件描述語言進(jìn)行設(shè)計(jì)描述，使用eda工具進(jìn)行功能仿真、綜合，并在fpga器件上完成了系統(tǒng)的硬件驗(yàn)證。 - ( 3 ) the paper researched two powerfully practical kinds of attempering method of high - level synthesis , which were based on function cell maximal utility rate and conditional structure
本文深入研究了實(shí)用性強(qiáng)的高級(jí)綜合的兩種調(diào)度算法，即基于功能單元最大利用率的調(diào)度算法和條件結(jié)構(gòu)的調(diào)度算法。 - 3 ) the paper discussed the theory and the method of asic high - level synthesis : ? nalyzed the synthesizable problems of vhdl language systematically , and discussed the establishment and the implementation methods of vhdl synthesis subclasses
3 )本文對asic高級(jí)綜合的理論與方法進(jìn)行了深入的探討：系統(tǒng)地分析了vhdl語言的可綜合性問題，并探討了vhdl綜合子集的確立及實(shí)現(xiàn)方法。 - ? he paper established a midst data format figured by high - level synthesis design , which is cdfg model , put forward the cdfg denotation of basic sentences in vhdl synthesis subclasses chose in the paper and gave out the automatic creation methods of cdfg
本文建立了一個(gè)高級(jí)綜合設(shè)計(jì)表示的中間數(shù)據(jù)格式，即cdfg模型，提出了本文所選定的vhdl綜合子集中基本語句的cdfg表示，給出了cdfg的自動(dòng)生成方法。 - High - level synthesis has been developed on the base of logic synthesis . it starts from the behavioral design description of high - level and outputs the structural description with lower level as a result . so the design complexity can be simplified and design efficiency can be raised
高級(jí)綜合是在邏輯綜合的基礎(chǔ)上發(fā)展而來的，它從高層次的行為描述開始，自動(dòng)綜合出低層次的結(jié)構(gòu)描述，從而降低了設(shè)計(jì)復(fù)雜度，提高了設(shè)計(jì)效率。 - Abstract : constant components and output opened ports in the result of high - level synthesis lead to explicit redundancy in gate - level technology mapping . explicit redundancy can not improve the performance , but increases power consumption , enlarges circuit area and decreases its testability , so it should be removed . this paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability
文摘:高級(jí)綜合結(jié)果中常量元件和輸出懸空端口導(dǎo)致門級(jí)工藝映射結(jié)果中存在顯式冗余.顯式冗余無助于提高電路性能，反而增加功耗，降低電路的可測試性，使電路面積增大，應(yīng)予消除.文中提出了顯式冗余的隊(duì)列循環(huán)優(yōu)化算法，完全消除了此類冗余，從而有效地減少了生成電路的基片面積，提高了電路的可測試性 - Now high - level design method based on high - level synthesis is a popular research project in the field of asic design and this kind of method has not been put into use completely , so the paper researches the asic design in the automation system of a kind of auv with high - level design method based on high - level synthesis and will devote to the development of eda technology of our country greatly
基于vhdl高級(jí)綜合的高層次設(shè)計(jì)方法是目前asic設(shè)計(jì)業(yè)普遍關(guān)注的熱點(diǎn)研究課題，該方法在國內(nèi)尚未達(dá)到實(shí)用化程度，因此本文采用該方法對水下航行器自控系統(tǒng)的集成設(shè)計(jì)進(jìn)行研究，將為我國eda技術(shù)的發(fā)展作出創(chuàng)造性的貢獻(xiàn)。